The present invention relates generally to computer memory, and more specifically to multi-write endurance and error control coding of non-volatile memories.
Phase-change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, program/erase cycles for flash memory), the memory cells wear out and can no longer reliably store information
One characteristic of contemporary NAND flash memory devices is that they do not support page erase. The absence of page erases, implies that once a page is written, it cannot be rewritten until the entire block (e.g., made up of sixty-four pages) is erased. If a logical address corresponding to a page needs to be refreshed, this is accomplished by marking the page as invalid and mapping the logical block address to a different physical page. Periodic garbage collection is required to be performed, where blocks with only a few valid pages are freed up by copying their valid pages to other physical pages, after which the block can be erased. This increases the number of writes required in a flash memory device, an effect that is often referred to as “write amplification”. Write amplification adversely affects the lifetime of the flash device due to the wear caused by the additional program/erase cycles.